Multilayer interconnection is required for medium/large scale integrated circuits. Traditional silicon metal oxide semiconductor field effect transistor (MOSFET) integrated circuits are typically based on a structure where active transistor devices are fabricated first, followed by back-end processing including multilayer metal interconnection line deposition. This integration scheme is ideal for traditional semiconductor transistors with top-gated structures and channel material which is intrinsically grown from the substrate wafer.
However, for semiconductor materials such as graphene- or carbon nanotube-based transistors, additional factors need to be considered when developing an integration scheme. First, in most cases, the graphene or carbon nanotubes are extrinsically deposited onto the substrate, and thus a bottom-gated structure is employed to render simpler processing and higher flexibility for semiconductor-dielectric interface engineering. Second, graphene and carbon nanotubes are very susceptible to damage and contamination from exposure to further processing. Thus, with graphene- or carbon nanotube-based devices it is desirable to minimize the exposure of the devices to subsequent processing.
Therefore, MOSFET integrated circuit fabrication techniques that are suitable for use with graphene- or carbon nanotube-based transistors, i.e., are compatible with both top- and bottom-gated devices and isolate the devices from processing damage and contamination, would be desirable.